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6 TPs sur Carte Basys3 (Artix-7) - De la LED au SoC

1

Prise en Main de Vivado

Premier projet FPGA - LED clignotante

⏱️ Duree: 3h 📚 Niveau: Debutant 🔧 Carte: Basys3 💻 Outil: Vivado
🎯
Objectifs

Maitriser le flot de conception FPGA complet: creation de projet, synthese, implementation, generation du bitstream et programmation.

Partie 1 : Creation du Projet Vivado

  1. Lancer Vivado > Create Project
  2. Nom: tp1_blink, RTL Project
  3. Selectionner la carte: Basys3 (xc7a35tcpg236-1)
  4. Creer un nouveau fichier source VHDL: blink.vhd

Partie 2 : Code VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity blink is
    port (
        clk  : in  std_logic;  -- 100 MHz
        led  : out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavioral of blink is
    signal counter : unsigned(26 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            counter <= counter + 1;
        end if;
    end process;
    
    -- LED0 clignote a ~0.75 Hz (100MHz / 2^27)
    led(0) <= counter(26);
    
    -- Chenillard sur les autres LEDs
    led(15 downto 1) <= std_logic_vector(counter(26 downto 12));
end architecture;

Partie 3 : Fichier de Contraintes (XDC)

Creer un fichier basys3.xdc dans Sources > Add Sources > Constraints

## Clock 100 MHz
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 -name sys_clk [get_ports clk]

## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3  [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3  [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3  [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3  [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3  [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1  [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1  [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]

Partie 4 : Synthese et Implementation

  1. Run Synthesis - Analyser les rapports
  2. Run Implementation - Verifier le timing
  3. Generate Bitstream - Creer le fichier .bit
  4. Open Hardware Manager - Programmer la carte
💡
Verification

Consultez toujours le rapport de timing. Le WNS (Worst Negative Slack) doit etre positif!

📝 A faire

  1. Modifier la frequence de clignotement (1 Hz, 2 Hz, 5 Hz)
  2. Creer un chenillard (Knight Rider) sur les 16 LEDs
  3. Analyser le rapport d'utilisation des ressources
2

Entrees Utilisateur

Switches, boutons et anti-rebond

⏱️ Duree: 3h 📚 Niveau: Debutant 🔧 Carte: Basys3

Partie 1 : Lecture des Switches

entity switches_leds is
    port (
        sw  : in  std_logic_vector(15 downto 0);
        led : out std_logic_vector(15 downto 0)
    );
end entity;

architecture behavioral of switches_leds is
begin
    led <= sw;  -- Copie directe
end architecture;

Contraintes Switches (Basys3)

## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
## ... (sw[2] a sw[15])

Partie 2 : Anti-Rebond (Debouncer)

entity debouncer is
    generic (DELAY : integer := 1000000);  -- 10ms @ 100MHz
    port (
        clk     : in  std_logic;
        btn_in  : in  std_logic;
        btn_out : out std_logic
    );
end entity;

architecture behavioral of debouncer is
    signal counter : integer range 0 to DELAY := 0;
    signal btn_reg : std_logic := '0';
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if btn_in /= btn_reg then
                counter <= 0;
                btn_reg <= btn_in;
            elsif counter < DELAY then
                counter <= counter + 1;
            else
                btn_out <= btn_reg;
            end if;
        end if;
    end process;
end architecture;

Contraintes Boutons (Basys3)

## Buttons
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
set_property PACKAGE_PIN T18 [get_ports btnU]
set_property IOSTANDARD LVCMOS33 [get_ports btnU]
set_property PACKAGE_PIN W19 [get_ports btnL]
set_property IOSTANDARD LVCMOS33 [get_ports btnL]
set_property PACKAGE_PIN T17 [get_ports btnR]
set_property IOSTANDARD LVCMOS33 [get_ports btnR]
set_property PACKAGE_PIN U17 [get_ports btnD]
set_property IOSTANDARD LVCMOS33 [get_ports btnD]

📝 A faire

  1. Implementer un compteur incremente par bouton (avec anti-rebond)
  2. Creer un selecteur de mode (switches) pour differents patterns LED
  3. Detecteur de front montant pour compter les appuis
3

Affichage 7 Segments

Multiplexage et affichage dynamique

⏱️ Duree: 4h 📚 Niveau: Intermediaire

Architecture du Multiplexage

    4 Afficheurs 7 segments (anodes communes)
    
    ┌─────┐ ┌─────┐ ┌─────┐ ┌─────┐
    │  3  │ │  2  │ │  1  │ │  0  │
    └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘
       │       │       │       │
       └───────┴───┬───┴───────┘
                   │
            ┌──────┴──────┐
            │  Segments   │  (cathodes communes)
            │  a,b,c,d,   │
            │  e,f,g,dp   │
            └─────────────┘
    
    Principe: Activer une seule anode a la fois
              et afficher le digit correspondant
              Frequence de rafraichissement > 50Hz

Contraintes 7 Segments (Basys3)

## 7-Segment Display Segments
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]  # CA
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]  # CB
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]  # CC
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]  # CD
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]  # CE
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]  # CF
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]  # CG
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

## 7-Segment Display Anodes
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]

📝 A faire

  1. Implementer le decodeur BCD vers 7 segments
  2. Creer le multiplexeur d'affichage (1 kHz)
  3. Afficher un compteur 0-9999 incremente chaque seconde
  4. Ajouter l'affichage hexadecimal (0-F)
4

Communication UART

Interface serie avec PC

⏱️ Duree: 4h 📚 Niveau: Avance

Specifications UART

  • Baudrate: 9600 bps
  • Format: 8N1 (8 bits, no parity, 1 stop)
  • Diviseur: 100 MHz / 9600 = 10417

Contraintes UART (Basys3 via USB)

## USB-UART Interface
set_property PACKAGE_PIN B18 [get_ports RsRx]
set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
set_property PACKAGE_PIN A18 [get_ports RsTx]
set_property IOSTANDARD LVCMOS33 [get_ports RsTx]

📝 A faire

  1. Implementer le transmetteur UART (echo des switches)
  2. Implementer le recepteur UART
  3. Creer un loopback complet
  4. Commander les LEDs depuis un terminal PC
5

Memoire et VGA

Block RAM et sortie video

⏱️ Duree: 5h 📚 Niveau: Avance

Interface VGA Basys3

## VGA Connector
set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
## ... (vgaGreen, vgaBlue)
set_property PACKAGE_PIN P19 [get_ports Hsync]
set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
set_property PACKAGE_PIN R19 [get_ports Vsync]
set_property IOSTANDARD LVCMOS33 [get_ports Vsync]

📝 A faire

  1. Generer les signaux de synchronisation VGA 640x480@60Hz
  2. Afficher des barres de couleur
  3. Stocker une image en Block RAM et l'afficher
  4. Creer un sprite mobile (controle par boutons)
6

Projet Final : Jeu Pong

Integration complete

⏱️ Duree: 6h 📚 Niveau: Expert

Specifications

  • Affichage VGA 640x480
  • 2 raquettes controlees par boutons
  • Balle avec rebonds
  • Score affiche sur 7 segments
  • Son sur buzzer (optionnel)

Architecture

┌─────────────────────────────────────────────────────────┐
│                      TOP LEVEL                           │
├──────────┬───────────┬───────────┬─────────────────────┤
│  VGA     │  Game     │  Score    │  Input              │
│  Timing  │  Logic    │  Display  │  Handler            │
│  Sync    │  (FSM)    │  7-seg    │  Debounce           │
├──────────┼───────────┼───────────┼─────────────────────┤
│  Ball    │  Paddle   │  Paddle   │  Collision          │
│  Ctrl    │  Left     │  Right    │  Detect             │
└──────────┴───────────┴───────────┴─────────────────────┘

📝 A faire

  1. Implementer le controleur VGA
  2. Creer les entites Ball et Paddle
  3. Implementer la detection de collision
  4. Ajouter la gestion du score
  5. Integrer le son (optionnel)
📌

Reference Rapide Basys3

Pinout et ressources

Ressources FPGA Artix-7 (xc7a35t)

RessourceQuantite
Logic Cells33,280
CLB Slices5,200
LUT20,800
Flip-Flops41,600
Block RAM50 x 36Kb = 1,800 Kb
DSP48E190
MMCM5

Travaux Pratiques FPGA | Electronique et Informatique Industrielle

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